Paper Abstract and Keywords |
Presentation |
2018-03-09 11:20
A 2.1μm 33Mpixel CMOS imager with multi-functional 3-stage pipeline ADC for 480fps high-speed mode and 120fps low-noise mode Kohei Tomioka, Toshio Yasue, Ryohei Funatsu, Tomohiro Nakamura (NHK STR), Takahiro Yamasaki (NHK Engineering Administration Department), Hiroshi Shimamoto (NHK STR), Tomohiko Kosugi, Sungwook Jun, Takashi Watanabe, Masanori Nagase, Toshiaki Kitajima, Satoshi Aoyama (Brookman Technology), Shoji Kawahito (Shizuoka University) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A 2.1μm 33Mpixel CMOS for 8K video is described. A novel column parallel 3-stage pipeline ADC composed of FI (Folding-Integration), dual-cyclic and SAR provides multiple operation modes. In the 120fps 14bit mode, the 6-times of sampling in the FI and digital CDS reduce random noise and VFPN to 3.2 e- and 0.24e-, respectively. In the 480fps mode, the dual-cyclic and SAR achieve 480fps operation. The dual-cyclic ADC has two sampling capacitors and omit feedback phase by using them alternately. We have developed an 8K 240fps single-chip high speed image capture equipment using this imager. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
8K SHV / CMOS imager / 3-stage pipeline ADC / 480fps / high speed imaging / low noise / / |
Reference Info. |
ITE Tech. Rep., vol. 42, no. 10, IST2018-15, pp. 17-20, March 2018. |
Paper # |
IST2018-15 |
Date of Issue |
2018-03-02 (IST) |
ISSN |
Print edition: ISSN 1342-6893 Online edition: ISSN 2424-1970 |
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