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Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
IEICE-ICD, IEICE-SDM, IST [detail] |
2022-08-08 16:20 |
Online |
On-line |
[Invited Talk]
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur Zule Xu, Masaru Osada, Tetsuya Iizuka (UTokyo) |
[more] |
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IST, IEICE-ICD |
2011-07-22 09:25 |
Hiroshima |
Hiroshima Institute of Technology |
An All-Digital On-Chip PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator Tetsuya Iizuka, Kunihiro Asada (Univ. of Tokyo) |
This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring o... [more] |
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IST, IEICE-ICD |
2010-07-22 10:45 |
Osaka |
Josho Gakuen Osaka Center |
Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Tetsuya Iizuka, Toru Nakura, Kunihiro Asada (Univ. of Tokyo) |
In this paper, we propose an all-digital process variability monitor which utilizes a simple buffer ring with a pulse co... [more] |
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