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All Technical Committee Conferences (Searched in: Recent 10 Years)
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| Search Results: Conference Papers |
| Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| IST |
2025-03-21
14:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online) |
Low Dark Noise and 8.5k e- Full Well Capacity in a 2-Layer Transistor Stacked 0.8μm Dual Pixel CIS with Intermediate Poly-Si Wiring
Yosuke Satake, Shinya Sato, Masayuki Takase, Mizuki Hoyano, Shuhei Kasukawa, Yusuke Tanaka, Yoshiaki Kitano, Manabu Tomita, Junpei Yamamoto, Kai Tokuhiro, Yoshiaki Kikuchi, Hirano Tomoyuki, Yoshiki Nishida (SSS) |
[more] |
IST2025-17
pp.32-36 |
| IST |
2022-09-22
13:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online) |
A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency
Chihiro Tomita, Koichiro Zaitsu, Akira Matsumoto, Mizuki Nishida, Yusuke Tanaka, Hirofumi Yamashita, Yusuke Satake (SSS), Takashi Watanabe, Kunihiko Araki, Naoki Nei (SCK), Keiichi Nakazawa, Junpei Yamamoto, Mutsuo Uehara (SSS), Hiroyuki Kawashima, Yusaku Kobayashi (SCK), Tomoyuki Hirano, Keiji Tatani (SSS) |
[more] |
IST2022-34
pp.1-4 |
| IEICE-ICD, IEICE-SDM, IST [detail] |
2022-08-08
09:00 |
Online |
On-line |
[Invited Talk]
A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency
Koichiro Zaitsu, Akira Matsumoto, Mizuki Nishida, Yusuke Tanaka, Hirofumi Yamashita, Yosuke Satake (Sony Semiconductor Solutions), Takashi Watanabe, Kunihiko Araki, Naoki Nei (Sony Semiconductor Manufacturing), Keiichi Nakazawa, Junpei Yamamoto, Mutsuo Uehara (Sony Semiconductor Solutions), Hiroyuki Kawashima, Yusaku Kobayashi (Sony Semiconductor Manufacturing), Tomoyuki Hirano, Keiji Tatani (Sony Semiconductor Solutions) |
[more] |
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| IST |
2022-03-28
09:55 |
Online |
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3D Sequential Process Integraton for CMOS Image Sensor
Keiichi Nakazawa, Junpei Yamamoto, Shigetaka Mori, Shintarou Okamoto, Akito Shimizu, Koichi Baba, Nobutoshi Fujii, Mutsuo Uehara, Katsunori Hiramatsu, Hideomi Kumano, Akira Matsumoto, Kouichirou Zaitsu, Hidetoshi Ohnuma, Keiji Tatani, Tomoyuki Hirano, Hayato Iwamoto (Sony Semconductor Solutions Corp.) |
We developed a new structure of pixel transistors stacked over photodiode named “2-Layer Transistor Pixel Stacked CMOS I... [more] |
IST2022-12
pp.9-12 |
| IST |
2021-03-26
12:50 |
Tokyo |
Online |
A Back Illuminated 10μm SPAD Pixel Array Comprising Full Trench Isolation and Cu-Cu Bonding with Over 14% PDE at 940nm
Kyosuke Ito, Yusuke Otake, Yoshiaki Kitano, Akira Matsumoto, Junpei Yamamoto, Takayuki Ogasahara, Hiroki Hiyama, Ryusei Naito, Kohei Takeuchi, Takanori Tada, Kosaku Takabayashi, Hajime Nakayama, Keiji Tatani, Tomoyuki Hirano, Toshifumi Wakano (SONY) |
A state of the art Back Illuminated (BI) Single Photon Avalanche Diode (SPAD) array sensor realized via a 90nm CMOS proc... [more] |
IST2021-14
pp.25-28 |
| IST |
2020-03-27
13:55 |
Tokyo |
Kikaishinko kaikan
(Postponed) |
Three-layer Stacked Color Image Sensor With 2.0-μm Pixel Size Using Organic Photoconductive Film
Taiichiro Watanabe, Hideaki Togashi, Masahiro Joei, Toshihiko Hayashi, Shintaro Hirata, Shinpei Fukuoka, Yoshihiro Ando, Yusuke Sato, Junpei Yamamoto, Iwao Yagi, Masaki Murata (SSS), Miki Kuribayashi (SONY), Fumihiko Koga, Tetsuji Yamaguchi, Yusuke Oike (SSS), Takayuki Ezaki, Teruo Hirayama (SONY) |
[more] |
IST2020-17
pp.41-45 |
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