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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 3 of 3  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IST 2026-03-27
13:10		 Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)		 Silicon-on-Insulator Pixel FinFET Technology for a High Conversion Gain and Low Dark Noise 2-Layer Transistor Pixel Stacked CIS
Ryohei Takayanagi, Takashi Kamo, Ryosuke Yamachi, Mayu Sakurai, Hidetoshi Oishi, Takuya Iriguchi, Hiroshi Takahashi, Taikei Enomoto, Yuki Kageyama, Yusuke Tanaka, Yoshiaki Kikuchi, Junpei Yamamoto, hideomi kumano, Shinichi Yoshida, Yoshiaki Kitano, Kazunobu Ohta, Tomoyuki Hirano (Sony Semiconductor Solutions) 		This study presents a 2-Layer transistor pixel stacked 0.8-µm dual-pixel (DP) CIS with silicon-on-insulator (SOI) fin fi... [more] IST2026-19
pp.40-43
IST 2025-03-21
14:35		 Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)		 Low Dark Noise and 8.5k e- Full Well Capacity in a 2-Layer Transistor Stacked 0.8μm Dual Pixel CIS with Intermediate Poly-Si Wiring
Yosuke Satake, Shinya Sato, Masayuki Takase, Mizuki Hoyano, Shuhei Kasukawa, Yusuke Tanaka, Yoshiaki Kitano, Manabu Tomita, Junpei Yamamoto, Kai Tokuhiro, Yoshiaki Kikuchi, Hirano Tomoyuki, Yoshiki Nishida (SSS) 		 [more] IST2025-17
pp.32-36
IST 2023-09-15
14:30		 Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)		 High Full Well Capacity and Low Noise Characteristics in 0.6 μm Pixels via Buried Sublocal Connections in a 2-Layer Transistor Pixel Stacked CMOS Imager Sensor
Keiji Nishida, Masataka Sugimoto, Tatsuya Okawa, Kanta Suzuki, Tomoharu Ogita, Katsunori Hiramatsu, Tomoyuki Hirano, Yoshiaki Kikuchi (SSS), Yuji Nishimura, Kohei Takeuchi, Daisuke Yoneyama, Toru Nagaki, Noriteru Yamada, Hiroyuki Kawashima (SCK), Yoshiaki Kitano (SSS) 		 [more] IST2023-42
pp.29-32
 Results 1 - 3 of 3  /   
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