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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IST 2021-03-26
09:25
Tokyo Online Evaluation of the effect of the 3D defect distribution created by plasma process on the dark current characteristics
Yoshihiro Sato, Takayoshi Yamada, Kazuko Nishimura, Masayuki Yamasaki, Masashi Murakami (Panasonic), Keiichiro Urabe, Koji Eriguchi (Kyoto Univ.)
Plasma processing is widely used in manufacturing present-day ULSI circuits. During plasma processing, defects are creat... [more] IST2021-9
pp.5-8
BCT, KYUSHU, IEEE-BT, IEEE-AP-S-FUKUOKA 2020-01-23
14:30
Kagoshima   Design of a Low-Loss Planar Magic-T Employing Rectangle DGS
Hiroki Nakahara, Takayuki Tanaka, Ichihiko Toyoda (Saga Univ.)
In this paper,a low-loss planar magic-T employing a Defected Ground Structure (DGS) is proposed.The proposed magic-T con... [more] BCT2020-5
pp.17-20
AIT, IIEEJ, AS 2015-03-14
15:15
Tokyo   Re-Color Scheme for Color Vision Defect Using Luminosity and Color Confusion Line
Shota Nakama, Koji Nishio, Ken-ichi Kobori (OIT)
Color information is an important means for information transmission. In general, color scheme is determined as an ordin... [more] AIT2015-43
pp.31-34
IST 2014-03-14
16:40
Tokyo NHK Low Noise Multi-aperture camera by Selective Averaging
Bo Zhang, Keiichiro Kagawa, Taishi Takasawa, Min-Woong Seo, Keita Yasutomi, Shoji Kawahito (Shizuoka Univ.)
A low noise multi-aperture camera which has a synthetic F-number much smaller than 1.0 by increasing optical gain using ... [more] IST2014-16
pp.31-34
IST, CE 2012-03-30 Tokyo Kikai-Shinko-Kaikan Bldg. Extremely-Low-Noise CMOS Image Sensor with High Saturation Capacity
Kazuichiroh Itonaga, Kyohei Mizuta, Toyotaka Kataoka, Harumi Ikeda, Masashii Yanagita, Hiroaki Ishiwata, Yusuke Tanaka, Takashi Wakano, Yoshihisa Matoba, Tetsuya Oishi, Ryou Yamamoto, Shinichi Arakawa, Jun Komachi, Mikio Katsumata, Shinya Watanabe (Sony)
We have developed a flat device structure, which we call “FLAT”, with no isolation grooves/ridges and no Si substrate et... [more]
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