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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IST 2024-03-27
15:05
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
An 0.08 e*pJ/step gain-adaptive single-slope ADC with enhanced HDR function for high-quality imagers
Luong Hung, Koji Matsuura, Hiroki Suto, Kazutoshi Kodama, Yosuke Tanaka, Toshiaki Ono, Junichiro Fujimagari, Miho Akahide, Yoshiaki Inada (Sony Semiconductor Solutions)
This paper, which was reported at IEEE Symposium on VLSI circuit 2023, presents a high-speed, power-efficient single-slo... [more] IST2024-20
pp.39-41
IEICE-SDM, IEICE-ICD, IST [detail] 2017-07-31
14:10
Hokkaido Hokkaido-Univ. Multimedia Education Bldg. Time variation reduction of shoot-through current for TDC+Single-Slope ADC architecture
Sayuri Yokoyama, Masayuki Ikebe, Sokuzinn Na, Shinya Takamaeda, Masato Motomura, Tetsuya Asai (Hokkaido Univ.)
We propose a Single-Slope ADC with a time to digital converter(TDC) that uses a quadrature-phase-detection instead of a ... [more] IST2017-42
pp.27-30
IST 2016-03-11
14:50
Tokyo NHK Research Lab (Setagaya) An 18M-pixel CMOS Image Sensor Using 12-bit Column-Parallel Single-Slope ADCs with Operation-Period-Reduced Time-to-Digital Converters
Yoshio Hagihara, Yusaku Koyama, Takanori Tanaka, Atsuko Kume, Yosuke Kusano, Mai Arita, Masashi Saito, Yoshihisa Okada (Olympus)
In this paper, we propose a 12-bit column-parallel single-slope (SS) ADC with operation-period-reduced time-to-digital c... [more] IST2016-16
pp.37-40
IST, IEICE-ICD 2012-07-27
09:50
Yamagata Yamagata University (Yonezawa) An interleaved ramp wave generator for High-speed single slope ADC
Daisuke Uchida, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano (Hokkaido Univ.), Akira Kondou (NJRC)
We have proposed the method of re-measuring quantizing error of Single-Slope ADC for CMOS imager with TDC (Time-to-Digit... [more] IST2012-36
pp.45-48
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