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Paper Abstract and Keywords
Presentation 2013-07-04 09:30
93% Power Reduction by Automatic Self Power Gating (ASPG) and Multistage Inverter for Negative Resistance (MINR) in 0.7V, 9.2uW, 39MHz Crystal Oscillator
Shunta Iguchi (Univ. of Tokyo), Akira Saito (STARC), Yunfei Zheng (Univ. of Tokyo), Kazunori Watanabe (STARC), Takayasu Sakurai, Makoto Takamiya (Univ. of Tokyo)
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Conference Information
Committee IST IEICE-ICD  
Conference Date 2013-07-04 - 2013-07-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Sun ref re Hakodate 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog circuits, Mixed signal, RF and Sensor I/F, etc. 
Paper Information
Registration To IEICE-ICD 
Conference Code 2013-07-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) 93% Power Reduction by Automatic Self Power Gating (ASPG) and Multistage Inverter for Negative Resistance (MINR) in 0.7V, 9.2uW, 39MHz Crystal Oscillator 
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1st Author's Name Shunta Iguchi  
1st Author's Affiliation University of Tokyo (Univ. of Tokyo)
2nd Author's Name Akira Saito  
2nd Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
3rd Author's Name Yunfei Zheng  
3rd Author's Affiliation University of Tokyo (Univ. of Tokyo)
4th Author's Name Kazunori Watanabe  
4th Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
5th Author's Name Takayasu Sakurai  
5th Author's Affiliation University of Tokyo (Univ. of Tokyo)
6th Author's Name Makoto Takamiya  
6th Author's Affiliation University of Tokyo (Univ. of Tokyo)
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Date Time 2013-07-04 09:30:00 
Presentation Time 25 minutes 
Registration for IEICE-ICD 
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Volume (vol) vol.37 
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