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Paper Abstract and Keywords
Presentation 2021-08-17 11:00
[Invited Talk] Development of 144-bit CMOS Annealing Processor with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems
Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Mashiro Mayumi, Masanao Yamaoka (Hitachi)
Abstract (in Japanese) (See Japanese page) 
(in English) (Not available yet)
Keyword (in Japanese) (See Japanese page) 
(in English) / / / / / / /  
Reference Info. ITE Tech. Rep.
Paper #  
Date of Issue  
ISSN Print edition: ISSN 1342-6893  Online edition: ISSN 2424-1970
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Conference Information
Committee IEICE-SDM IEICE-ICD IST  
Conference Date 2021-08-17 - 2021-08-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Online 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications 
Paper Information
Registration To IEICE-ICD 
Conference Code 2021-08-SDM-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of 144-bit CMOS Annealing Processor with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems 
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1st Author's Name Takashi Takemoto  
1st Author's Affiliation Hitachi Ltd. (Hitachi)
2nd Author's Name Kasho Yamamoto  
2nd Author's Affiliation Hitachi Ltd. (Hitachi)
3rd Author's Name Chihiro Yoshimura  
3rd Author's Affiliation Hitachi Ltd. (Hitachi)
4th Author's Name Mashiro Mayumi  
4th Author's Affiliation Hitachi Ltd. (Hitachi)
5th Author's Name Masanao Yamaoka  
5th Author's Affiliation Hitachi Ltd. (Hitachi)
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Speaker
Date Time 2021-08-17 11:00:00 
Presentation Time 45 
Registration for IEICE-ICD 
Paper #  
Volume (vol) ITE-45 
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