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Paper Abstract and Keywords
Presentation 2022-02-22 14:25
Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction
Kohei Shinyamada, Akira Yamawaki (Kyutech)
Abstract (in Japanese) (See Japanese page) 
(in English) In this study, we developed a median-based dynamic background subtraction image processing system equipped with a real camera. The hardware was developed using high-level synthesis. We evaluated the performance of the developed hardware alone, and found that the performance was 166 fps for the image size QVGA and the number of time-series images N=4. The hardware processing was superior in terms of power efficiency when compared to the embedded CPU. However, since the frame rate of the camera used in the prototype was approximately 12 fps, the maximum frame rate of the entire system was approximately 12 fps.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / High-Level Synthesis / HLS / Image Processing / Real Camera System / / /  
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Conference Information
Committee AIT ME MMS IEICE-IE IEICE-ITS  
Conference Date 2022-02-21 - 2022-02-22 
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Paper Information
Registration To IEICE-IE 
Conference Code 2022-02-IE-ITS-AIT-ME-MMS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) High-Level Synthesis  
Keyword(3) HLS  
Keyword(4) Image Processing  
Keyword(5) Real Camera System  
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1st Author's Name Kohei Shinyamada  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Akira Yamawaki  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
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Speaker Author-1 
Date Time 2022-02-22 14:25:00 
Presentation Time 15 minutes 
Registration for IEICE-IE 
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Volume (vol) vol.46 
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