| Paper Abstract and Keywords |
| Presentation |
2024-03-27 15:30
A 3.36 µm-pitch SPAD photon-counting image sensor using clustered multi-cycle clocked recharging technique with intermediate most-significant-bit readout
Takafumi Takatsuka, Jun Ogi, Yasuji Ikeda, Kazuki Hizu, Yutaka Inaoka, Shunsuke Sakama, Iori Watanabe, Tatsuya Ishikawa, Shohei Shimada, Junki Suzuki (SSS), Hidenori Maeda, Kenji Toshima (SCK), Yusuke Nonaka, Akifumi Yamamura, Hideki Ozawa, Fumihiko Koga, Yusuke Oike (SSS) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper introduces the pixel front-end (PFE) circuit pitch reduction of SPAD photon count image sensor, which was reported at 2023 Symposium on VLSI Technology and Circuits [8]. A SPAD photon count image sensor with 120-dB High Dynamic Range (HDR) at 3.36 µm-pitch was realized. Conventionally, the SPAD photon count image sensor for realizing HDR has been limited to a PFE circuit pitch of about 10 μm, but the counter circuit in PFE circuit of 8 bits was realized by using a clustered multi-cycle clocked recharging (CMCR) technique with intermediate most-significant-bit readout (MSB-Read). Furthermore, the maximum utilization of the fine logic (22 nm) due to the amplitude limitation reduced the PFE circuit pitch. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
CMOS image sensors / photon-counting / ingle-photon avalanche diode / 3D stack / high dynamic range / / / |
| Reference Info. |
ITE Tech. Rep., vol. 48, no. 15, IST2024-21, pp. 42-45, March 2024. |
| Paper # |
IST2024-21 |
| Date of Issue |
2024-03-20 (IST) |
| ISSN |
Online edition: ISSN 2424-1970 |
| Download PDF |
|