| Paper Abstract and Keywords |
| Presentation |
2026-08-04 15:40
Fault Injection into KV Cache of an FPGA-based Transformer and Its Evaluation
Ryo Kumagai, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This study focuses on the KV cache that maintained during autoregressive generation in Transformer inference and evaluates the impact of data corruption which can occur in hardware inference environments on generation results. While the KV cache accelerates inference by reusing the Key and Value of past tokens, it represents an intermediate state that possesses a fault propagation path distinct from that of model weights or activations. In this study, we target Transformer inference engine implemented on an FPGA, inject single-element faults into the KV cache, and analyze output variations by comparing the results against fault-free generated sequences. Experimental results confirm that even a single-word fault can alter subsequent generated sequences and that the distinct roles of Keys and Values are reflected in the nature of the output corruption. These findings demonstrate the necessity of treating the KV cache as a target for protection in Transformer accelerators operating in wild devices. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
large language models / FPGA / fault injection / KV cache / Transformer accelerator / / / |
| Reference Info. |
ITE Tech. Rep. |
| Paper # |
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| Date of Issue |
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| ISSN |
Online edition: ISSN 2424-1970 |
| Download PDF |
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| Conference Information |
| Committee |
IEICE-ICD IEICE-SDM IST |
| Conference Date |
2026-08-04 - 2026-08-06 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Hokkaido Univ, Pharmaceutical Sciences, Lecture Room 2 |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Paper Information |
| Registration To |
IEICE-ICD |
| Conference Code |
2026-08-ICD-SDM-IST |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Fault Injection into KV Cache of an FPGA-based Transformer and Its Evaluation |
| Sub Title (in English) |
|
| Keyword(1) |
large language models |
| Keyword(2) |
FPGA |
| Keyword(3) |
fault injection |
| Keyword(4) |
KV cache |
| Keyword(5) |
Transformer accelerator |
| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Ryo Kumagai |
| 1st Author's Affiliation |
Meijo University (Meijo Univ.) |
| 2nd Author's Name |
Shu Takemoto |
| 2nd Author's Affiliation |
Meijo University (Meijo Univ.) |
| 3rd Author's Name |
Yusuke Nozaki |
| 3rd Author's Affiliation |
Meijo University (Meijo Univ.) |
| 4th Author's Name |
Masaya Yoshikawa |
| 4th Author's Affiliation |
Meijo University (Meijo Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2026-08-04 15:40:00 |
| Presentation Time |
25 minutes |
| Registration for |
IEICE-ICD |
| Paper # |
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| Volume (vol) |
vol.50 |
| Number (no) |
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| Page |
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| #Pages |
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