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Committee Date Time Place Paper Title / Authors Abstract Paper #
IST 2017-03-10
Tokyo NHK Research Lab. Auditorium (Setagaya) A 1ms High-Speed Vision Chip with 3D-Stacked 140GOPS Column-Parallel PEs for Spatio-Temporal Image Processing
Masatsugu Kobayashi, Tomohiro Yamazaki, Hironobu Katayama, Shuji Uehara, Atsushi Nose, Sayaka Shida (Sony Semiconductor Solutions Co.), Masaki Odahara, Kenichi Takamiya, Yasuaki Hisamatsu, Shizunori Matsumoto (Sony LSI Design Inc.), Leo Miyashita, Yoshihiro Watanabe (University of Tokyo), Takashi Izawa, Yoshinori Muramatsu (Sony Semiconductor Solutions Co.), Masatoshi Ishikawa (University of Tokyo)
We have developed a 1/3.2-inch 1.27Mpixel 500fps (0.31Mpixel 1000fps 2×2 binning) vision chip with 3D-stacked CMOS image... [more] IST2017-9
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