ITE Technical Group Submission System
Conference Schedule |
Online Proceedings
[Sign in]
|
|
|
|
|
All Technical Committee Conferences (Searched in: All Years)
|
|
|
| Search Results: Conference Papers |
| Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
|
|
| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| IST |
2026-03-27
13:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online) |
Silicon-on-Insulator Pixel FinFET Technology for a High Conversion Gain and Low Dark Noise 2-Layer Transistor Pixel Stacked CIS
Ryohei Takayanagi, Takashi Kamo, Ryosuke Yamachi, Mayu Sakurai, Hidetoshi Oishi, Takuya Iriguchi, Hiroshi Takahashi, Taikei Enomoto, Yuki Kageyama, Yusuke Tanaka, Yoshiaki Kikuchi, Junpei Yamamoto, hideomi kumano, Shinichi Yoshida, Yoshiaki Kitano, Kazunobu Ohta, Tomoyuki Hirano (Sony Semiconductor Solutions) |
This study presents a 2-Layer transistor pixel stacked 0.8-µm dual-pixel (DP) CIS with silicon-on-insulator (SOI) fin fi... [more] |
IST2026-19
pp.40-43 |
| IST |
2014-03-14
12:00 |
Tokyo |
NHK |
Three-dimensional Structures for High Saturation Signals and Crosstalk Suppression in 1.20 um Pixel Back-Illuminated CMOS Image Sensor
Takekazu Shinohara, Kazufumi Watanabe (Sony Semiconductor), Takashi Abe, Kazunobu Ohta (Sony), Hajime Nakayama (Sony Semiconductor), Takafumi Morikawa, Keiichi Ohno (Sony), Dai Sugimoto (Sony Semiconductor), Shingo Kadomura, Teruo Hirayama (Sony) |
We propose two technologies, vertical transfer gate (VTG) and buried shielding metal (BSM), that can be applied to 1.20 ... [more] |
IST2014-10
pp.7-10 |
|
|
|
|
|
[Return to Top Page]
[Return to ITE Web Page]
|