This paper presents a 187.5µVrms read noise, 51mW, 17fps, 1.4MPixel CMOS image sensor in a 0.13µm CMOS technology. To reduce the area and the power consumption of column CDS circuits, 1.5V PMOSCAPS with body terminal control are employed. We propose a 10b self-differential offset-cancelled pipeline SAR-ADC. It operates with reference voltage of ADC’s half full-scale voltage, leading to 80% switching power and 50% CDAC area reduction in ADC. Black-level correction is built in the ADC without any additional DACs.