Paper Abstract and Keywords |
Presentation |
0000-00-00 00:00
A 187.5uVrms-Read-Noise 51mW 1.4Mpixel CMOS Image Sensor with PMOSCAP Column CDS and 10b Self-Differential Offset-Cancelled Pipeline SAR-ADC Jun Deguchi, Fumihiko Tachibana, Makoto Morimoto, Masayoshi Chiba (Toshiba), Takeshi Miyaba (Toshiba Microelectronics), Hideki Tanaka (Toshiba), Kyoichi Takenaka (Toshiba Microelectronics), Satoshi Funayama, Kunihiko Amano, Kazuhide Sugiura, Ryuta Okamoto, Shouhei Kousai (Toshiba) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a 187.5µVrms read noise, 51mW, 17fps, 1.4MPixel CMOS image sensor in a 0.13µm CMOS technology. To reduce the area and the power consumption of column CDS circuits, 1.5V PMOSCAPS with body terminal control are employed. We propose a 10b self-differential offset-cancelled pipeline SAR-ADC. It operates with reference voltage of ADC’s half full-scale voltage, leading to 80% switching power and 50% CDAC area reduction in ADC. Black-level correction is built in the ADC without any additional DACs. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
PMOSCAP column CDS / Pipeline SAR-ADC / Differential-offset Control / / / / / |
Reference Info. |
ITE Tech. Rep. |
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