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Paper Abstract and Keywords
Presentation 2012-07-27 09:50
An interleaved ramp wave generator for High-speed single slope ADC
Daisuke Uchida, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano (Hokkaido Univ.), Akira Kondou (NJRC)
Abstract (in Japanese) (See Japanese page) 
(in English) We have proposed the method of re-measuring quantizing error of Single-Slope ADC for CMOS imager with TDC (Time-to-Digital Converter). Using n-bits TDC, the proposed ADC performed 2n time faster operation. This method requires high-speed Ramp wave generation. Therefore, in this paper, we evaluated speed up with interleave operation and output summing of DACs. Although multiple DACs are used, there is no increase of quantization unit devices. In the interleaved DAC with 2n-m of m-bits DAC units, it can perform as a Delta DAC (-2l≦Vout≦2m-l). We designed fabricated the current-controlled DAC circuits using 0.18um CMOS process. At 100-MHz-clock operation, we confirmed 400-MHz 12-bit operations with four of 10-bits DAC units. The circuit was able to achieve DNL of +0.5/–0.5 LSB and INL of +0.7/–0.8 LSB. The entire generator consumed 5.58 mW with a 1.8-V supply.
Keyword (in Japanese) (See Japanese page) 
(in English) Single-Slope ADC / interleave operation / Multi-Phase Clock / / / / /  
Reference Info. ITE Tech. Rep., vol. 36, no. 31, IST2012-36, pp. 45-48, July 2012.
Paper # IST2012-36 
Date of Issue 2012-07-20 (IST) 
ISSN Print edition: ISSN 1342-6893
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Conference Information
Committee IST IEICE-ICD  
Conference Date 2012-07-26 - 2012-07-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Yamagata University (Yonezawa) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed analog and digital, RF, and sensor interface circuitry 
Paper Information
Registration To IST 
Conference Code 2012-07-IST-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An interleaved ramp wave generator for High-speed single slope ADC 
Sub Title (in English)  
Keyword(1) Single-Slope ADC  
Keyword(2) interleave operation  
Keyword(3) Multi-Phase Clock  
1st Author's Name Daisuke Uchida  
1st Author's Affiliation Hokkaido University (Hokkaido Univ.)
2nd Author's Name Masayuki Ikebe  
2nd Author's Affiliation Hokkaido University (Hokkaido Univ.)
3rd Author's Name Junichi Motohisa  
3rd Author's Affiliation Hokkaido University (Hokkaido Univ.)
4th Author's Name Eiichi Sano  
4th Author's Affiliation Hokkaido University (Hokkaido Univ.)
5th Author's Name Akira Kondou  
5th Author's Affiliation NJRC (NJRC)
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Speaker Author-1 
Date Time 2012-07-27 09:50:00 
Presentation Time 25 minutes 
Registration for IST 
Paper # IST2012-36 
Volume (vol) vol.36 
Number (no) no.31 
Page pp.45-48 
Date of Issue 2012-07-20 (IST) 

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