Paper Abstract and Keywords |
Presentation |
2014-03-14 11:30
3D Stacked CMOS Image Sensor Taku Umebayashi, Tomoharu Ogita, Shunichi Sukegawa, Tsutomu Nakajima, Hiroshi Kawanobe (Sony), Ken Koseki (Sony LSI Design), Tsutomu Haruta, Hiroshi Takahashi (Sony), Keishi Inoue (Sony Semiconductor), Toshifumi Wakano, Yusuke Mada, Koji Fukumoto, Takashi Nagano, Yoshikazu Nitta, Teruo Hirayama (Sony) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have developed 3D stacked CMOS image sensor. This technology is a Back-illuminated CIS stacking on a logic substrate. The electrical connections between CIS and logic use the through silicon via (TSV) contacts. By implementing this structure, the chip size is reduced and secures a circuit area on the logic substrate. New functions added on the circuit area have improved imaging quality such as high dynamic range (HDR) movie and clear image zoom. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS image sensor / Back-illuminated CIS / Three-dimensional Stacking / Small chip size / TSV / HDR / / |
Reference Info. |
ITE Tech. Rep., vol. 38, no. 15, IST2014-9, pp. 5-5, March 2014. |
Paper # |
IST2014-9 |
Date of Issue |
2014-03-07 (IST) |
ISSN |
Print edition: ISSN 1342-6893 |
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