| Paper Abstract and Keywords |
| Presentation |
2016-03-11 11:40
A 1.1μm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters
Toshiki Arai, Toshio Yasue, Kazuya Kitamura, Hiroshi Shimamoto (NHK STRL), Tomohiko Kosugi, Sungwook Jun, Satoshi Aoyama (Brookman Technology), Ming-Chieh Hsu, Yuichiro Yamashita (TSMC), Hirofumi Sumi (The University of Tokyo), Shoji Kawahito (Shizuoka University) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
A 1.1μm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based ADC has been developed. The hybrid-stacking technology connects the pixels and an arrayed ADC in the pixel area. The pipelined operation of the cyclic-cyclic-SAR ADC effectively reduces the conversion time period to 0.92 μs. The ADC architecture and the hybrid-stacking technology achieve a high frame rate of 240 fps in 33 Mpixels. A random noise of 3.6 e- and sensor power consumption of 3.0 W are attained at an extremely high pixel rate of 7.96 Gpixel/s. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
8K SHV / 33Mpixel / 240fps / 3-stage ADC / 3D-stacked / hybrid-stacking technology / / |
| Reference Info. |
ITE Tech. Rep., vol. 40, no. 12, IST2016-12, pp. 21-24, March 2016. |
| Paper # |
IST2016-12 |
| Date of Issue |
2016-03-04 (IST) |
| ISSN |
Print edition: ISSN 1342-6893 Online edition: ISSN 2424-1970 |
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