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Paper Abstract and Keywords
Presentation 2016-03-11 11:40
A 1.1μm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters
Toshiki Arai, Toshio Yasue, Kazuya Kitamura, Hiroshi Shimamoto (NHK STRL), Tomohiko Kosugi, Sungwook Jun, Satoshi Aoyama (Brookman Technology), Ming-Chieh Hsu, Yuichiro Yamashita (TSMC), Hirofumi Sumi (The University of Tokyo), Shoji Kawahito (Shizuoka University)
Abstract (in Japanese) (See Japanese page) 
(in English) A 1.1μm 33Mpixel 240fps 3D-stacked CMOS image sensor with 3-stage cyclic-based ADC has been developed. The hybrid-stacking technology connects the pixels and an arrayed ADC in the pixel area. The pipelined operation of the cyclic-cyclic-SAR ADC effectively reduces the conversion time period to 0.92 μs. The ADC architecture and the hybrid-stacking technology achieve a high frame rate of 240 fps in 33 Mpixels. A random noise of 3.6 e- and sensor power consumption of 3.0 W are attained at an extremely high pixel rate of 7.96 Gpixel/s.
Keyword (in Japanese) (See Japanese page) 
(in English) 8K SHV / 33Mpixel / 240fps / 3-stage ADC / 3D-stacked / hybrid-stacking technology / /  
Reference Info. ITE Tech. Rep., vol. 40, no. 12, IST2016-12, pp. 21-24, March 2016.
Paper # IST2016-12 
Date of Issue 2016-03-04 (IST) 
ISSN Print edition: ISSN 1342-6893  Online edition: ISSN 2424-1970
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Conference Information
Committee IST  
Conference Date 2016-03-11 - 2016-03-11 
Place (in Japanese) (See Japanese page) 
Place (in English) NHK Research Lab (Setagaya) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Solid state image sensors, etc. 
Paper Information
Registration To IST 
Conference Code 2016-03-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 1.1μm 33Mpixel 240fps 3D-Stacked CMOS Image Sensor with 3-Stage Cyclic-Based Analog-to-Digital Converters 
Sub Title (in English)  
Keyword(1) 8K SHV  
Keyword(2) 33Mpixel  
Keyword(3) 240fps  
Keyword(4) 3-stage ADC  
Keyword(5) 3D-stacked  
Keyword(6) hybrid-stacking technology  
Keyword(7)  
Keyword(8)  
1st Author's Name Toshiki Arai  
1st Author's Affiliation NHK Science & Technology Research Laboratories (NHK STRL)
2nd Author's Name Toshio Yasue  
2nd Author's Affiliation NHK Science & Technology Research Laboratories (NHK STRL)
3rd Author's Name Kazuya Kitamura  
3rd Author's Affiliation NHK Science & Technology Research Laboratories (NHK STRL)
4th Author's Name Hiroshi Shimamoto  
4th Author's Affiliation NHK Science & Technology Research Laboratories (NHK STRL)
5th Author's Name Tomohiko Kosugi  
5th Author's Affiliation Brookman Technology Inc. (Brookman Technology)
6th Author's Name Sungwook Jun  
6th Author's Affiliation Brookman Technology Inc. (Brookman Technology)
7th Author's Name Satoshi Aoyama  
7th Author's Affiliation Brookman Technology Inc. (Brookman Technology)
8th Author's Name Ming-Chieh Hsu  
8th Author's Affiliation Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)
9th Author's Name Yuichiro Yamashita  
9th Author's Affiliation Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)
10th Author's Name Hirofumi Sumi  
10th Author's Affiliation The University of Tokyo (The University of Tokyo)
11th Author's Name Shoji Kawahito  
11th Author's Affiliation Shizuoka University (Shizuoka University)
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Speaker
Date Time 2016-03-11 11:40:00 
Presentation Time 25 
Registration for IST 
Paper # ITE-IST2016-12 
Volume (vol) ITE-40 
Number (no) no.12 
Page pp.21-24 
#Pages ITE-4 
Date of Issue ITE-IST-2016-03-04 


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