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Paper Abstract and Keywords
Presentation 2016-08-01 10:00
A fast-start up and fully-integrated 32-MHz clock generator for intermittent VLSI systems
Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) This paper proposes a fully integrated 32-MHz relaxation oscillator (ROSC)
capable of fast start-up time operation for low-power intermittent VLSI
systems. The proposed ROSC employs current mode architecture that is
different from conventional voltage mode architecture. This enables compact
and fast switching speed to be achieved. By designing transistor sizes
equally between one in a bias circuit and another in a voltage to current
converter, the effect of process variation can be minimized. A prototype
chip in a 0.18-um CMOS demonstrated that the ROSC generates a stable
clock frequency of 32.6 MHz within 1-us start-up time. Measured line
regulation and temperature coefficient were ±0.69% and ±0.38%,
Keyword (in Japanese) (See Japanese page) 
(in English) Relaxation Oscillator (ROSC) / Fast start-up / Digital signal processing / Intermittent operation / High accuracy / PVT variation / /  
Reference Info. ITE Tech. Rep.
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Conference Information
Conference Date 2016-08-01 - 2016-08-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Central Electric Club 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low voltage/low power techniques, novel devices, circuits, and applications 
Paper Information
Registration To IEICE-ICD 
Conference Code 2016-08-ICD-SDM-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A fast-start up and fully-integrated 32-MHz clock generator for intermittent VLSI systems 
Sub Title (in English)  
Keyword(1) Relaxation Oscillator (ROSC)  
Keyword(2) Fast start-up  
Keyword(3) Digital signal processing  
Keyword(4) Intermittent operation  
Keyword(5) High accuracy  
Keyword(6) PVT variation  
1st Author's Name Hiroki Asano  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Tetsuya Hirose  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Taro Miyoshi  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Keishi Tsubaki  
4th Author's Affiliation Kobe University (Kobe Univ.)
5th Author's Name Toshihiro Ozaki  
5th Author's Affiliation Kobe University (Kobe Univ.)
6th Author's Name Nobutaka Kuroki  
6th Author's Affiliation Kobe University (Kobe Univ.)
7th Author's Name Masahiro Numa  
7th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker Author-1 
Date Time 2016-08-01 10:00:00 
Presentation Time 25 minutes 
Registration for IEICE-ICD 
Paper #  
Volume (vol) vol.40 
Number (no)  
Date of Issue  

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