| Paper Abstract and Keywords |
| Presentation |
2018-07-27 10:55
A Min-Sum LDPC Decoder with Variable Parallelism and Its Memory Bank Access Scheduling Method
Taishi Watanabe, Hiroshi Tsutsui (Hokkaido Univ.), Takashi Imagawa (Ritsumeikan Univ.), Yoshikazu Miyanaga (Hokkaido Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Recently, LDPC (low-density parity-check) codes have been widely used in various applications including 5G wireless communication systems due to its powerful error-correcting capability. Considering its decoder design, since one design cannot be the optimum for all applications and devices, we need to design a dedicated LDPC decoder of each specific standardized parity check matrix for each application and device, which requires high design costs. Moreover, in the processing of LDPC decoders, the memory access conflict is a serious issue as one of the reasons limiting its throughput. Motivated by this, we are aiming to establish a framework that automatically generates an RTL implementation based on a baseline architecture considering the required performance under given design constraints. In this paper, we propose a min-sum LDPC decoder with variable parallelism and its memory bank access scheduling method. We demonstrate the proposed approach showing a fully parallel implementation of an LDPC decoder utilizing row parallel processing and column parallel processing and its half parallelism version. Experimental results show that the fully parallel implementation archives an output throughput of 800Mbps with 3.13M required gates and that its half parallelism version archives 282.4Mbps with 1.80M gates. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
LDPC code / min-sum decoding / parallel processing / / / / / |
| Reference Info. |
ITE Tech. Rep., vol. 42, no. 23, BCT2018-71, pp. 47-50, July 2018. |
| Paper # |
BCT2018-71 |
| Date of Issue |
2018-07-19 (BCT) |
| ISSN |
Print edition: ISSN 1342-6893 Online edition: ISSN 2424-1970 |
| Download PDF |
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| Conference Information |
| Committee |
BCT IEEE-BT HOKKAIDO |
| Conference Date |
2018-07-26 - 2018-07-27 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Hokkaido Univ. |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Broadcast Operating Technologies, Transmission & Reception Engineering, etc. |
| Paper Information |
| Registration To |
BCT |
| Conference Code |
2018-07-BCT-BT-HOKKAIDO |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A Min-Sum LDPC Decoder with Variable Parallelism and Its Memory Bank Access Scheduling Method |
| Sub Title (in English) |
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| Keyword(1) |
LDPC code |
| Keyword(2) |
min-sum decoding |
| Keyword(3) |
parallel processing |
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| 1st Author's Name |
Taishi Watanabe |
| 1st Author's Affiliation |
Hokkaido University (Hokkaido Univ.) |
| 2nd Author's Name |
Hiroshi Tsutsui |
| 2nd Author's Affiliation |
Hokkaido University (Hokkaido Univ.) |
| 3rd Author's Name |
Takashi Imagawa |
| 3rd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name |
Yoshikazu Miyanaga |
| 4th Author's Affiliation |
Hokkaido University (Hokkaido Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2018-07-27 10:55:00 |
| Presentation Time |
25 minutes |
| Registration for |
BCT |
| Paper # |
BCT2018-71 |
| Volume (vol) |
vol.42 |
| Number (no) |
no.23 |
| Page |
pp.47-50 |
| #Pages |
4 |
| Date of Issue |
2018-07-19 (BCT) |