| Paper Abstract and Keywords |
| Presentation |
2019-03-22 10:00
Noise Suppression Effect of Folding-Integration Applied to a column-parallel 3-stage pipeline ADC in a 2.1 μm 33-megapixel CMOS Image sensor
Kohei Tomioka, Kohei Tomioka, Yasue Toshio, Ryohei Funatsu, Tomoki Matsubara (NHK STRL), Tomohiko Kosugi, Sungwook Jun, Takashi Watanabe, Masanori Nagase, Toshiaki Kitajima, Satoshi Aoyama (Brookman Technology), Shoji Kawahito (Shizuoka University) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This study investigated the noise suppression effect of multiple sampling applied to a 3-stage pipeline analog-to-digital converter (ADC) in a 33-megapixel, 120-fps 1.25-in CMOS image sensor. The 3-stage pipeline ADC is composed of folding-integration (FI), cyclic, and successive approximation register ADCs, and the multiple sampling for noise suppression is implemented in the FI ADC. The sampling number M is limited by the conversion interval of the FI ADC and the maximum sampling number is M = 6 at the 120-fps operation. To investigate the noise suppression effect of 120-fps operation, we measured the random noise of the pixel readout circuit to the sampling number M and compared with theoretical calculations. As a result, we confirmed that the measurement result corresponds reasonably well with the calculated result and the sampling number M = 6 is effective for noise suppression. Furthermore, the calculations revealed that the influence of 1/f noise of the source follower is dominant on the noise performance. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
UHDTV / 8K / Image Sensor / Noise Suppression / CMS / Folding-Integration / 3-stage pipeline ADC / |
| Reference Info. |
ITE Tech. Rep., vol. 43, no. 11, IST2019-14, pp. 11-16, March 2019. |
| Paper # |
IST2019-14 |
| Date of Issue |
2019-03-15 (IST) |
| ISSN |
Print edition: ISSN 1342-6893 Online edition: ISSN 2424-1970 |
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