Paper Abstract and Keywords |
Presentation |
2021-10-21 15:00
Noise reduction by using sample-and-hold circuits for bias voltage of pixel source followers Kohei Tomioka, Toshio Yasue, Kodai Kikuchi, Tomohiro Nakamura, Takayuki Yamashita, Kazuya Kitamura (NHK STRL), Shoji Kawahito (Shizuoka Univ.) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A bias voltage generation method was proposed for a pixel source follower amplifier which is suitable for high resolution and high frame rate complementary metal-oxide semiconductor (CMOS) image sensors. In this method, the local bias circuit in every column and the sample-and-hold function for the gate voltage of the load transistor were used to prevent shading and streaking noise, while realizing low noise and high speed performance of the pixel source follower. The theoretical noise analysis of an 8K 120 fps image sensor with the proposed method showed a low input-referred noise of 2.04 e^−, whereas, the conventional method showed noise of 2.57 e^−. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS image sensor / High-resolution / High-framerate / Noise reduction / / / / |
Reference Info. |
ITE Tech. Rep., vol. 45, no. 30, IST2021-59, pp. 45-48, Oct. 2021. |
Paper # |
IST2021-59 |
Date of Issue |
2021-10-14 (IST) |
ISSN |
Print edition: ISSN 1342-6893 Online edition: ISSN 2424-1970 |
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