| 講演抄録／キーワード |
| 講演名 |
2022-03-28 09:05
A 4.9Mpixel Programmable-Resolution Multi-Purpose CMOS Image Sensor for Computer Vision
○Hirotaka Murakami・Eric Bohannon・John Childs・Grace Gui・Eric Moule（SEL）・Katsuhiko Hanzawa（SSS）・Tomofumi Koda（SEL）・Chiaki Takano（SSS）・Toshimasa Shimizu・Yuki Takizawa（SLSI）・Adarsh Basavalingappa・Robert Childs・Cody Cziesler・Robert Jarnot（SEL）・Kazumasa Nishimura（SLSI）・Scott Rogerson・Yoshikazu Nitta（SEL） |
| 抄録 |
（和） |
Today’s mobile devices are capable of multiple tasks, including viewing and computer vision. However, these tasks are often implemented using multiple cameras due to divergent requirements, resulting in increases in form factor. Higher resolutions and frame rates are required to take pictures and video, while lower resolutions and frame rates are preferred especially for always-on computer vision to save power. To reduce the form factor, this paper presents a single-chip solution where both high-resolution viewing images and lower-resolution computer vision images are generated from one CMOS Image sensor (CIS). Full field-of-view programmable image resolutions are made possible with floating-diffusion (FD) binning through serial switches. In-frame dynamic voltage and frequency scaling (DVFS) is applied to minimize power at lower pixel resolutions and frame rates. 1/2, 1/4, 1/8, 1/16 and 1/192 binning modes are demonstrated using a 2560(H)×1920(V) pixel array that, at 1fps, consumes 790µW for full-color VGA and 120µW for motion-detection (MD) mode. |
| （英） |
Today’s mobile devices are capable of multiple tasks, including viewing and computer vision. However, these tasks are often implemented using multiple cameras due to divergent requirements, resulting in increases in form factor. Higher resolutions and frame rates are required to take pictures and video, while lower resolutions and frame rates are preferred especially for always-on computer vision to save power. To reduce the form factor, this paper presents a single-chip solution where both high-resolution viewing images and lower-resolution computer vision images are generated from one CMOS Image sensor (CIS). Full field-of-view programmable image resolutions are made possible with floating-diffusion (FD) binning through serial switches. In-frame dynamic voltage and frequency scaling (DVFS) is applied to minimize power at lower pixel resolutions and frame rates. 1/2, 1/4, 1/8, 1/16 and 1/192 binning modes are demonstrated using a 2560(H)×1920(V) pixel array that, at 1fps, consumes 790µW for full-color VGA and 120µW for motion-detection (MD) mode. |
| キーワード |
（和） |
Low Power CMOS Image Sensor / Programmable-Resolution / Dynamic Voltage and Frequency Scaling / / / / / |
| （英） |
/ / / / / / / |
| 文献情報 |
映情学技報, vol. 46, no. 14, IST2022-10, pp. 1-4, 2022年3月. |
| 資料番号 |
IST2022-10 |
| 発行日 |
2022-03-21 (IST) |
| ISSN |
Print edition: ISSN 1342-6893 Online edition: ISSN 2424-1970 |
| PDFダウンロード |
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