Paper Abstract and Keywords |
Presentation |
2022-03-28 09:55
3D Sequential Process Integraton for CMOS Image Sensor Keiichi Nakazawa, Junpei Yamamoto, Shigetaka Mori, Shintarou Okamoto, Akito Shimizu, Koichi Baba, Nobutoshi Fujii, Mutsuo Uehara, Katsunori Hiramatsu, Hideomi Kumano, Akira Matsumoto, Kouichirou Zaitsu, Hidetoshi Ohnuma, Keiji Tatani, Tomoyuki Hirano, Hayato Iwamoto (Sony Semconductor Solutions Corp.) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We developed a new structure of pixel transistors stacked over photodiode named “2-Layer Transistor Pixel Stacked CMOS Image Sensor” (2-Layer Pixel). It was fabricated by 3D sequential process integration with new process techniques, such as thermally stable wafer bonding and deep contacts. With this technology, we successfully increased AMP size and demonstrated backside-illuminated CMOS image sensor of 6752 x 4928 pixels at 0.7um pitch to prove its functionality and integrity. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
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Reference Info. |
ITE Tech. Rep., vol. 46, no. 14, IST2022-12, pp. 9-12, March 2022. |
Paper # |
IST2022-12 |
Date of Issue |
2022-03-21 (IST) |
ISSN |
Print edition: ISSN 1342-6893 Online edition: ISSN 2424-1970 |
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