Paper Abstract and Keywords |
Presentation |
2022-03-28 09:30
3-Layer Stacked Pixel-Parallel CMOS Image Sensors Using Hybrid Bonding of SOI Wafers Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi (NHK), Takuya Saraya, Masaharu Kobayashi (The Univ. of Tokyo), Eiji Higurashi (AIST), Hiroshi Toshiyoshi, Toshiro Hiramoto (The Univ. of Tokyo) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We report 3-layer stacked pixel-parallel CMOS image sensors developed for the first time. The hybrid bonding of silicon-on-insulator (SOI) wafers through embedded Au electrodes in the SiO2 insulators on the front and back sides realizes both face-to-face and face-to-back bonding, realizing a multi-layer stacked device. A 3-layered pixel circuit is developed to confirm the linear response of 16-bit digital signal output. A prototype sensor with 160 × 120 pixels successfully captures video images, demonstrating the feasibility of multi-layered sensors of high performance as well as multi-functions including signal processing, memory, and computing for applications such as high-quality video cameras, measurements, recognition, robots, and various IoT devices. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS image sensor / 3D integration / bonding / silicon-on-insulator (SOI) / A/D converter / / / |
Reference Info. |
ITE Tech. Rep., vol. 46, no. 14, IST2022-11, pp. 5-8, March 2022. |
Paper # |
IST2022-11 |
Date of Issue |
2022-03-21 (IST) |
ISSN |
Print edition: ISSN 1342-6893 Online edition: ISSN 2424-1970 |
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