Paper Abstract and Keywords |
Presentation |
2025-03-21 16:20
A 400×400 3.24µm 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor Tsung-Hsun Tsai (Meta), Kwuang-Han Chang (Brillnics), Andrew Berkovich, Raffaele Capoccia, Song Chen, Zhao Wang, Chiao Liu (Meta), Yi-Hsuan Lin, ShengYeh Lai, Hao-Ming Hsu, Hirofumi Abe, Kazuya Mori, Hideyuki Fukuhara, Chih-Hao Lin, Toshiyuki Isozaki, Wei-Chen Li, Wei-Fan Chou, Masayuki Uno, Rimon Ikeno, Masato Nagamatsu, Guang Yang, Shou-Gwo Wuu (Brillnics) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents 400×400 digital pixel sensor (DPS) with a 3.24µm pixel developed with a 3 layer-stacked process for AR/VR applications. This sensor achieves the smallest pixel pitch in DPS with in-pixel ADC circuit using a single-ended comparator and 10-bit in-pixel SRAM. The digital circuit layer (third layer) includes a frame memory for FPN correction, an image signal processor (ISP) and a capability to output multiple regions for low power consumption in tracking operations. The sensor achieves 117dB dynamic range in a single exposure with time to saturation (TTS) to overwrapped electron while consuming 3.06mW, a noise floor of 4.4e-rms, and a dark FPN of 2.4e-rms. The die size is 2.47×1.85mm² meeting the stringent form factor requirement of AR/VR devices. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOS image sensor / Digital pixel sensor / Global shutter / 3-Layer stacked / Sparse transmission / / / |
Reference Info. |
ITE Tech. Rep., vol. 49, no. 13, IST2025-21, pp. 53-57, March 2025. |
Paper # |
IST2025-21 |
Date of Issue |
2025-03-14 (IST) |
ISSN |
Online edition: ISSN 2424-1970 |
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