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Paper Abstract and Keywords
Presentation 2025-11-21 13:30
[Invited Talk] A Novel 1/1.3-inch 50 Megapixel three-wafer-stacked CMOS Image Sensor with DNN Circuit for Edge Processing 
Ryoichi Nakamura, Hidenobu Tsugawa, Wataru Otsuka, Kan Shimizu, Yoshihisa Kagawa, Kenta Ono, Yosuke Horie (Sony Semiconductor Solutions)
Abstract (in Japanese) (See Japanese page) 
(in English) This study reports the first ever 3-wafer-stacked CMOS image sensor comprising an artificial intelligence (AI) chip with a deep neural network (DNN)-based circuit. The sensor was fabricated by bonding wafer with a DNN-based circuit to the bottom of a conventional 2-layer-stacked image sensor using the wafer-on-wafer-on-wafer process. This process allowed the sensor to retain excellent imaging characteristics without affecting those of the top and middle wafers. This novel image sensor comprising a DNN can enhance the gate scale and incorporate the high dynamic range (HDR) function. Moreover, the pixelarray area can be expanded to approximately the same size as that of the chip to realize a resolution of 50 MP. Thus, the proposed sensor can perform DNN processing on higher resolution HDR image data than the conventional DNN-equipped 2-layer-stacked image sensor, resulting in remarkably improved image-recognition and high-performance edge processing with a single chip.
Keyword (in Japanese) (See Japanese page) 
(in English) 3-wafer-stacked CMOS image sensor / deep neural network / image-recognition / high dynamic range / / / /  
Reference Info. ITE Tech. Rep., vol. 49, no. 34, IST2025-46, pp. 1-4, Nov. 2025.
Paper # IST2025-46 
Date of Issue 2025-11-14 (IST) 
ISSN Online edition: ISSN 2424-1970
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Conference Information
Committee IST  
Conference Date 2025-11-21 - 2025-11-21 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To IST 
Conference Code 2025-11-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Novel 1/1.3-inch 50 Megapixel three-wafer-stacked CMOS Image Sensor with DNN Circuit for Edge Processing  
Sub Title (in English)  
Keyword(1) 3-wafer-stacked CMOS image sensor  
Keyword(2) deep neural network  
Keyword(3) image-recognition  
Keyword(4) high dynamic range  
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1st Author's Name Ryoichi Nakamura  
1st Author's Affiliation Sony Semiconductor Solutions Corporation (Sony Semiconductor Solutions)
2nd Author's Name Hidenobu Tsugawa  
2nd Author's Affiliation Sony Semiconductor Solutions Corporation (Sony Semiconductor Solutions)
3rd Author's Name Wataru Otsuka  
3rd Author's Affiliation Sony Semiconductor Solutions Corporation (Sony Semiconductor Solutions)
4th Author's Name Kan Shimizu  
4th Author's Affiliation Sony Semiconductor Solutions Corporation (Sony Semiconductor Solutions)
5th Author's Name Yoshihisa Kagawa  
5th Author's Affiliation Sony Semiconductor Solutions Corporation (Sony Semiconductor Solutions)
6th Author's Name Kenta Ono  
6th Author's Affiliation Sony Semiconductor Solutions Corporation (Sony Semiconductor Solutions)
7th Author's Name Yosuke Horie  
7th Author's Affiliation Sony Semiconductor Solutions Corporation (Sony Semiconductor Solutions)
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Speaker Author-1 
Date Time 2025-11-21 13:30:00 
Presentation Time 30 minutes 
Registration for IST 
Paper # IST2025-46 
Volume (vol) vol.49 
Number (no) no.34 
Page pp.1-4 
#Pages 4 
Date of Issue 2025-11-14 (IST) 

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