| Paper Abstract and Keywords |
| Presentation |
2026-06-22 10:00
A Low-Resource Image Classification Architecture for On-Chip Processing Based on Feature-Extractable CMOS Image Sensors
Ryoya Iegaki, Hiroki Morita, Yu Osuka (Ritsumeikan Univ.), Kota Yoshida (AIST/Ritsumeikan Univ.), Yohei Hori (AIST), Shunsuke Okura (Ritsumeikan Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
To reduce the power consumption of edge devices, we propose an image classification architecture that integrates in-sensor feature extraction of two-dimensional edge and luminance information, along with a lightweight RaScaNet model composed of CNN and RNN. This approach reduces the image data size to only 1.04% of that of color images, while limiting the classification accuracy degradation to 6.86%. Furthermore, by downsizing the RaScaNetto accommodate the quantized features, we achieved a model size of 5.1 KB and a peak memory of 0.9 KB, resulting in an approximately 300-fold reduction relative to MobileNetV2. Simulation results showed accuracies of 73.78% on the VWW dataset and 91.45% on the INRIA Person dataset. Additionally, we confirmed that the total memory footprint fits within the 3-line buffer capacity (5.7 KB) of conventional image sensors, quantitatively demonstrating the feasibility of on-chip computing in ultra-low resource environments. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
CMOS image sensor / feature extraction / On-Chip Processing / quantization / Low-Resource / / / |
| Reference Info. |
ITE Tech. Rep., vol. 50, no. 17, IST2026-28, pp. 1-6, June 2026. |
| Paper # |
IST2026-28 |
| Date of Issue |
2026-06-15 (IST, ME) |
| ISSN |
Online edition: ISSN 2424-1970 |
| Download PDF |
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| Conference Information |
| Committee |
IST ME IEICE-IE IEICE-BioX IEICE-SIP IEICE-MI |
| Conference Date |
2026-06-22 - 2026-06-23 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
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| Paper Information |
| Registration To |
IST |
| Conference Code |
2026-06-IST-ME-IE-BioX-SIP-MI |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A Low-Resource Image Classification Architecture for On-Chip Processing Based on Feature-Extractable CMOS Image Sensors |
| Sub Title (in English) |
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| Keyword(1) |
CMOS image sensor |
| Keyword(2) |
feature extraction |
| Keyword(3) |
On-Chip Processing |
| Keyword(4) |
quantization |
| Keyword(5) |
Low-Resource |
| Keyword(6) |
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| Keyword(7) |
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| 1st Author's Name |
Ryoya Iegaki |
| 1st Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name |
Hiroki Morita |
| 2nd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
| 3rd Author's Name |
Yu Osuka |
| 3rd Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name |
Kota Yoshida |
| 4th Author's Affiliation |
National Institute of Advanced Industrial Science and Technology/Ritsumeikan University (AIST/Ritsumeikan Univ.) |
| 5th Author's Name |
Yohei Hori |
| 5th Author's Affiliation |
National Institute of Advanced Industrial Science and Technology (AIST) |
| 6th Author's Name |
Shunsuke Okura |
| 6th Author's Affiliation |
Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2026-06-22 10:00:00 |
| Presentation Time |
25 minutes |
| Registration for |
IST |
| Paper # |
IST2026-28, ME2026-51 |
| Volume (vol) |
vol.50 |
| Number (no) |
no.17 |
| Page |
pp.1-6 |
| #Pages |
6 |
| Date of Issue |
2026-06-15 (IST, ME) |