| Paper Abstract and Keywords |
| Presentation |
2026-08-04 10:00
[Invited Talk]
Further Scaling of the Capacitance Equivalent Thickness (CET) In High-k/Metal Gate Stacks Toward the 2nm Technology Node and Beyond: Prospects and Challenges
Yukinori Morita, Takamasa Kawanago, Takefumi Kamioka (AIST/LSTC), Yuichiro Mitani (Tokyo City Univ./LSTC), Toshihide Nabatame, Takashi Onaya, Naoki Fukata, Wipakorn Jevasuwan, Kazuhito Tsukagoshi (NIMS/LSTC), Takuya Hoshii (Science Tokyo/LSTC), Kasidit Toprasertpong, Atsushi Tamura, Koji Kita (The Univ. Tokyo/LSTC), Naoya Okada, Kenzo Manabe, Wataru Mizubayashi, Hiroyuki Ota, Takashi Matsukawa, Shinji Migita (AIST/LSTC) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Scaling of the capacitance equivalent thickness (CET) of high-k/metal gate stacks remains a great challenge, even for advanced gate-all-around field-effect transistors at the sub-2-nm technology nodes. In the IRDS roadmap, the requirement value of CET for gate stacks is thinned down to 1 nm or less in the advanced node technology. In this study, prospects and challenges associated with further CET scaling are investigated through a combination of strategies involving the permittivity enhancement of high-k dielectrics and ultimate thinning of the interfacial layer (IL). |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
High-k / Metal gate / Gate stack / CET / HfO2 / ZrO2 / 界面層 / |
| Reference Info. |
ITE Tech. Rep. |
| Paper # |
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| Date of Issue |
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| ISSN |
Online edition: ISSN 2424-1970 |
| Download PDF |
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