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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 3 of 3  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
IST 2021-03-26
12:50		 Tokyo Online A Back Illuminated 10μm SPAD Pixel Array Comprising Full Trench Isolation and Cu-Cu Bonding with Over 14% PDE at 940nm
Kyosuke Ito, Yusuke Otake, Yoshiaki Kitano, Akira Matsumoto, Junpei Yamamoto, Takayuki Ogasahara, Hiroki Hiyama, Ryusei Naito, Kohei Takeuchi, Takanori Tada, Kosaku Takabayashi, Hajime Nakayama, Keiji Tatani, Tomoyuki Hirano, Toshifumi Wakano (SONY) 		A state of the art Back Illuminated (BI) Single Photon Avalanche Diode (SPAD) array sensor realized via a 90nm CMOS proc... [more] IST2021-14
pp.25-28
IST 2018-03-09
12:00		 Tokyo NHK Housou-Gijyutu Lab. [Invited Talk] Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology
Hidenobu Tsugawa, Hiroshi Takahashi, Ryoichi Nakamura, Taku Umebayashi, Tomoharu Ogita, Hitoshi Okano, Kazuya Iwase, Hiroyuki Kawashima, Takatsugu Yamasaki, Daisuke Yoneyama, Jun Hashizume, Tsutomu Nakajima, Kenichi Murata, Yoshikazu Kanaishi, Kenji Ikeda, Keiji Tatani, Hajime Nakayama, Tsutomu Haruta, Tetsuo Nomoto (Sony) 		 [more] IST2018-17
pp.25-29
IST 2014-03-14
12:00		 Tokyo NHK Three-dimensional Structures for High Saturation Signals and Crosstalk Suppression in 1.20 um Pixel Back-Illuminated CMOS Image Sensor
Takekazu Shinohara, Kazufumi Watanabe (Sony Semiconductor), Takashi Abe, Kazunobu Ohta (Sony), Hajime Nakayama (Sony Semiconductor), Takafumi Morikawa, Keiichi Ohno (Sony), Dai Sugimoto (Sony Semiconductor), Shingo Kadomura, Teruo Hirayama (Sony) 		We propose two technologies, vertical transfer gate (VTG) and buried shielding metal (BSM), that can be applied to 1.20 ... [more] IST2014-10
pp.7-10
 Results 1 - 3 of 3  /   
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