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Paper Abstract and Keywords
Presentation 2026-03-27 13:10
Silicon-on-Insulator Pixel FinFET Technology for a High Conversion Gain and Low Dark Noise 2-Layer Transistor Pixel Stacked CIS
Ryohei Takayanagi, Takashi Kamo, Ryosuke Yamachi, Mayu Sakurai, Hidetoshi Oishi, Takuya Iriguchi, Hiroshi Takahashi, Taikei Enomoto, Yuki Kageyama, Yusuke Tanaka, Yoshiaki Kikuchi, Junpei Yamamoto, hideomi kumano, Shinichi Yoshida, Yoshiaki Kitano, Kazunobu Ohta, Tomoyuki Hirano (Sony Semiconductor Solutions)
Abstract (in Japanese) (See Japanese page) 
(in English) This study presents a 2-Layer transistor pixel stacked 0.8-µm dual-pixel (DP) CIS with silicon-on-insulator (SOI) fin field-effect transistor (FinFET) technology. The application of SOI FinFETs as pixel transistors, featuring a body-less configuration on buried oxide, reduces parasitic capacitance at the floating diffusion node, thereby enhancing conversion gain and noise characteristics. The SOI FinFET achieves improved transconductance and source follower gain compared to a previous pixel FinFET. The resolution of challenges associated with the SOI structure is demonstrated through a 0.8μm DP CIS with SOI FinFETs.
Keyword (in Japanese) (See Japanese page) 
(in English) 2-Layer Transistor Pixel Stacked CIS / SOI Pixel FinFET / High Conversion Gain / Low Dark Noise / / / /  
Reference Info. ITE Tech. Rep., vol. 50, no. 14, IST2026-19, pp. 40-43, March 2026.
Paper # IST2026-19 
Date of Issue 2026-03-20 (IST) 
ISSN Online edition: ISSN 2424-1970
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Conference Information
Committee IST  
Conference Date 2026-03-27 - 2026-03-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To IST 
Conference Code 2026-03-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Silicon-on-Insulator Pixel FinFET Technology for a High Conversion Gain and Low Dark Noise 2-Layer Transistor Pixel Stacked CIS 
Sub Title (in English)  
Keyword(1) 2-Layer Transistor Pixel Stacked CIS  
Keyword(2) SOI Pixel FinFET  
Keyword(3) High Conversion Gain  
Keyword(4) Low Dark Noise  
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1st Author's Name Ryohei Takayanagi  
1st Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
2nd Author's Name Takashi Kamo  
2nd Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
3rd Author's Name Ryosuke Yamachi  
3rd Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
4th Author's Name Mayu Sakurai  
4th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
5th Author's Name Hidetoshi Oishi  
5th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
6th Author's Name Takuya Iriguchi  
6th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
7th Author's Name Hiroshi Takahashi  
7th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
8th Author's Name Taikei Enomoto  
8th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
9th Author's Name Yuki Kageyama  
9th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
10th Author's Name Yusuke Tanaka  
10th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
11th Author's Name Yoshiaki Kikuchi  
11th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
12th Author's Name Junpei Yamamoto  
12th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
13th Author's Name hideomi kumano  
13th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
14th Author's Name Shinichi Yoshida  
14th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
15th Author's Name Yoshiaki Kitano  
15th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
16th Author's Name Kazunobu Ohta  
16th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
17th Author's Name Tomoyuki Hirano  
17th Author's Affiliation Sony Semiconductor Solutions Corp. (Sony Semiconductor Solutions)
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Speaker Author-3 
Date Time 2026-03-27 13:10:00 
Presentation Time 25 minutes 
Registration for IST 
Paper # IST2026-19 
Volume (vol) vol.50 
Number (no) no.14 
Page pp.40-43 
#Pages 4 
Date of Issue 2026-03-20 (IST) 

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