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Technical Group on Information Sensing Technologies (IST) [schedule] [select]
Chair Junichi Akita (Kanazawa Univ.)
Vice Chair Masayuki Ikebe (Hokkaido Univ.)

Technical Committee on Silicon Device and Materials (IEICE-SDM) [schedule] [select]
Chair Shunichiro Ohmi (Tokyo Inst. of Tech.)
Vice Chair Tatsuya Usami (ASM Japan)
Secretary Tomoyuki Suwa (Tohoku Univ.), Taiji Noda (Panasonic)
Assistant Takuji Hosoi (Kwansei Gakuin Univ.), Takuya Futase (SanDisk)

Technical Committee on Integrated Circuits and Devices (IEICE-ICD) [schedule] [select]
Chair Masafumi Takahashi (Kioxia)
Vice Chair Makoto Ikeda (Univ. of Tokyo)
Secretary Kosuke Miyaji (Shinshu Univ.), Koji Nii (TSMC)
Assistant Jun Shiomi (Osaka Univ.), Yoshiaki Yoshihara (キオクシア), Takeshi Kuboki (Sony Semiconductor Solutions)

Conference Date Mon, Aug 8, 2022 09:00 - 17:05
Tue, Aug 9, 2022 09:20 - 14:50
Wed, Aug 10, 2022 09:00 - 16:10
Topics Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications 
Conference Place  
Sponsors This conference is co-sponsored by IEEE SSCS Japan Chapter, IEEE SSCS Kansai Chapter and The Japan Society of Applied Physics.
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on IST.

Mon, Aug 8 AM  Image Sensor
Chair: TBD
09:00 - 11:30
(1)
IEICE-SDM
09:00-09:45 [Invited Talk]
A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency
Koichiro Zaitsu, Akira Matsumoto, Mizuki Nishida, Yusuke Tanaka, Hirofumi Yamashita, Yosuke Satake (Sony Semiconductor Solutions), Takashi Watanabe, Kunihiko Araki, Naoki Nei (Sony Semiconductor Manufacturing), Keiichi Nakazawa, Junpei Yamamoto, Mutsuo Uehara (Sony Semiconductor Solutions), Hiroyuki Kawashima, Yusaku Kobayashi (Sony Semiconductor Manufacturing), Tomoyuki Hirano, Keiji Tatani (Sony Semiconductor Solutions)
(2)
IEICE-SDM
09:45-10:30 [Invited Talk]
Low-Noise Multi-Gate Pixel Transistor for Sub-Micron Pixel CMOS Image Sensors
Naohiko Kimizuka, Shota Kitamura, Akiko Honjo, Koichi Baba, Toshihiro Kurobe, Hideomi Kumano, Takuya Toyohuku (Sony Semiconductor Solutions), Kouhei Takeuchi, Shota Nishimura (Sony Semiconductor Manufacturing), Akihiko Kato, Tomoyuki Hirano, Yusuke Oike (Sony Semiconductor Solutions)
  10:30-10:45 Break ( 15 min. )
(3)
IEICE-ICD
10:45-11:30 [Invited Talk]
0.37 W, 143 dB Dynamic Range 1 Megapixel Backside-Illuminated Charge Focusing SPAD Image Sensor with Pixel-Wise Exposure Control and Adaptive Clocked Recharging
Yu Maehashi, Yasuharu Ota, Kazuhiro Morimoto, Tomoya Sasago, Mahito Shinohara, Yukihiro Kuroda, Wataru Endo, Shintaro Maekawa, Masanao Motoyama, Kenzo Tojima, Hiroyuki Tsuchiya, Ayman Abdelghafar, Kosei Uehira, Junji Iwata, Fumihiro Inui, Yasushi Matsuno, Katsuhito Sakurai, Takeshi Ichikawa (Canon)
Mon, Aug 8 AM  Memory Devices
Chair: TBD
11:30 - 12:15
(4)
IEICE-SDM
11:30-12:15 [Invited Talk]
Optimal Cell Structure/Operation Design of 3D Semicircular Split-gate Cells for Ultra-high-density Flash Memory
Tetsu Morooka (Kioxia)
  12:15-13:15 ( 60 min. )
Mon, Aug 8 PM  Ultra Low-Power
Chair: TBD
13:15 - 14:50
(5)
IEICE-ICD
13:15-14:00 [Invited Talk]
Research on Steep Slope "PN-Body Tied SOI-FET" for Ultra Low Power LSI
Jiro Ida, Takayuki Mori (Kanazawa IT)
(6)
IEICE-SDM
14:00-14:25 Evaluation of Steep Subthreshold Slope Device "Dual-gate PN-body Tied SOI-FET" for Ultra-low Voltage Operation Haruki Yonezaki, Jiro Ida, Takayuki Mori (KIT), Koichiro Ishibashi (UEC)
(7)
IEICE-ICD
14:25-14:50 Sub-50-mV Input Boost Converter for Extremely Low-Voltage Thermal Energy Harvesting Hikaru Sebe, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ.)
  14:50-15:05 Break ( 15 min. )
Mon, Aug 8 PM  Security & Analog1
Chair: TBD
15:05 - 17:05
(8)
IEICE-ICD
15:05-15:30 Evaluation of Backside Voltage Disturbance Impacts and IC Chip Response in Flip Chip Packaging Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa (Kobe Univ.), Kikuo Muramatsu (e-SYNC), Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo (Megachips), Takuji Miki, Makoto Nagata (Kobe Univ.)
(9)
IEICE-ICD
15:30-15:55 Evaluation of Low-Latency Cryptography MANTIS based Low-Power oriented Tamper-Resistant Circuit Kosuke Hamaguchi, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(10)
IEICE-ICD
15:55-16:20 A cryogenic digital-to-analog converter for high-fidelity control of large-scale qubit arrays Ryozo Takahashi, Takuji Miki, Makoto Nagata (Kobe Univ.)
(11)
IEICE-ICD
16:20-17:05 [Invited Talk]
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur
Zule Xu, Masaru Osada, Tetsuya Iizuka (UTokyo)
Tue, Aug 9 AM  Sensor & Cryogenic CMOS
Chair: TBD
09:20 - 12:15
(12)
IEICE-ICD
09:20-10:05 [Invited Talk]
A low-power low-noise magnetoimpedance-based magnetometer with digital calibration technique
Ippei Akita (AIST), Takeshi Kawano, Hitoshi Aoyama, Shunichi Tatematsu (Aichi Steel Corp.), Masakazu Hioki (AIST)
(13)
IEICE-ICD
10:05-10:50 [Invited Talk]
A 38µm Range Precision Time-of-Flight CMOS Range Line Imager with Gating Driver Jitter Reduction Using Charge-Injection Pseudo Photocurrent Reference
Keita Yasutomi, Tatsuki Furuhashi, Koki Sagawa, Taishi Takasawa, Keiichiro Kagawa, Shoji Kawahito (Shizuoka Univ.)
  10:50-11:05 Break ( 15 min. )
(14)
IEICE-SDM
11:05-11:50 [Invited Talk]
Effect of Conduction Band Edge States on Coulomb-Limiting Electron Mobility in Cryogenic MOSFET Operation
Hiroshi Oka, Takumi Inaba, Shota Iizuka, Hidehiro Asai, Kimihiko Kato, Takahiro Mori (AIST)
(15)
IEICE-SDM
11:50-12:15 TCAD Analysis for threshold voltage increase in cryogenic MOSFET operation Hidehiro Asai, Takumi Inaba, Junichi Hattori, Koichi Fukuda, Hiroshi Oka, Takahiro Mori (AIST)
  12:15-13:15 ( 60 min. )
Tue, Aug 9 PM  Sensor Application
Chair: TBD
13:15 - 14:50
(16)
IST
13:15-14:00 [Invited Talk]
Quantification of perception using Psychophysical Methods
Sae Kaneko (Hokkaido Univ.)
(17)
IST
14:00-14:25 High-precision small capacitance difference measurement using proximity capacitance sensor Yoshiaki Watanabe, Yuki Sugama, Yoshinobu Shiba, Rihito Kuroda, Yasuyuki Shirai, Shigetoshi Sugawa (Tohoku Univ.)
(18)
IST
14:25-14:50 Evaluation of simultaneous depth and stress measurement by array sensing using indenter physics Ayato Nozu, Rikuo Yugeta, Yuri Kanazawa, Masayuki Ikebe (Hokkaido Univ.)
Wed, Aug 10 AM  Analog 2
Chair: TBD
09:00 - 12:15
(19)
IEICE-ICD
09:00-09:45 [Invited Talk]
A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station
Zheng Li, Jian Pang, Yi Zhang, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Zhengyan Guo, Yun Wang, Xi Fu, Dongwon You (Tokyo Tech), Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro (NEC), Atsushi Shirane, Kenichi Okada (Tokyo Tech)
(20)
IEICE-ICD
09:45-10:30 [Invited Talk]
A Power-Efficient Harmonic-Selection Phased-Array Receiver Supporting 24.25-71GHz Operation With 36dB Inter-Band Blocker Rejection
Jian Pang, Yi Zhang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada (Tokyo Tech)
  10:30-10:45 Break ( 15 min. )
(21)
IEICE-ICD
10:45-11:30 [Invited Talk]
Low Power and Radiation-Hardened Ka-Band Transceiver for Small Satellite
Atsushi Shirane (Tokyo Tech)
(22)
IEICE-ICD
11:30-12:15 [Invited Talk]
A 28-GHz Fully-Passive Retro-Reflective Phased-Array Backscattering Transceiver for 5G Network with 24-GHz Beam-Steered Wireless Power Transfer
Michihiro Ide, Keito Yuasa, Sena Kato, Dongwon You, Ashbir Aviat Fadila, Jian Pang, Atsushi Shirane, Kenichi Okada (Titech)
  12:15-13:15 ( 60 min. )
Wed, Aug 10 PM  AI & Neural Network
Chair: TBD
13:15 - 16:10
(23)
IEICE-ICD
13:15-14:00 [Invited Talk]
Introducing a new DNN inference chip (Hiddenite) based on hidden network theory
Masato Motomura (TokyoTech)
(24)
IST
14:00-14:45 [Invited Talk]
Algorithm-architecture co-optimization for edge AI applications
Kota Ando (Hokkaido Univ.)
  14:45-15:00 Break ( 15 min. )
(25)
IEICE-ICD
15:00-15:45 [Invited Talk]
A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems
Fukashi Morishita, Norihito Kato, Satoshi Okubo, Takao Toi, Mitsuru Hiraki, Sugako Otani, Hideaki Abe, Yuji Shinohara, Hiroyuki Kondo (Renesas Electronics)
(26)
IEICE-ICD
15:45-16:10 IC with Integrated Imager and Ultra-Low Latency All-Digital In-Imager 2D Binary Convolutional Neural Network Accelerator for Image Classification Wang Ruizhi, Takamiya Makoto (The Univ. of Tokyo)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.
Invited TalkEach speech will have 40 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
IST Technical Group on Information Sensing Technologies (IST)   [Latest Schedule]
Contact Address  
IEICE-SDM Technical Committee on Silicon Device and Materials (IEICE-SDM)   [Latest Schedule]
Contact Address SDM Secretary: MORI Takahiro(National Institute of AIST)
Tel +81-29-849-1149
E-Mail -aist 
IEICE-ICD Technical Committee on Integrated Circuits and Devices (IEICE-ICD)   [Latest Schedule]
Contact Address Koji Nii (TSMC Design Technology Japan)
E-: ig 


Last modified: 2022-07-27 17:23:15


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