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Technical Committee on Integrated Circuits and Devices (IEICE-ICD) (Searched in: 2016)
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Search Results: Keywords 'from:2016-08-01 to:2016-08-01'
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| [Go to Official IEICE-ICD Homepage (Japanese)] |
| Search Results: Conference Papers |
| Conference Papers (Available on Advance Programs) (Sort by: Date Ascending) |
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| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| IEICE-ICD, IEICE-SDM, IST [detail] |
2016-08-03
11:25 |
Osaka |
Central Electric Club |
[Invited Talk]
A three-terminal spin-orbit torque switching magnetic memory device
Shunsuke Fukami, Tetsuro Anekawa, Ayato Ohkawara, Chaoliang Zhang, Hideo Ohno (Tohoku Univ.) |
Integrated circuits with non-volatile spintronics memory devices open up new pathways toward ultralow-power and high-per... [more] |
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| IEICE-ICD, IEICE-SDM, IST [detail] |
2016-08-03
13:20 |
Osaka |
Central Electric Club |
[Invited Talk]
A 16nm FinFET Heterogeneous Nona-Core SoC Supporting Functional Safety Standard ISO26262 ASIL B
Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji (Renesas System Design), Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita (Renesas Electronics) |
[more] |
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| IEICE-ICD, IEICE-SDM, IST [detail] |
2016-08-03
14:15 |
Osaka |
Central Electric Club |
Impacts of Flexible V_th control and Low Process Variability of SOTB to Ultra-low Voltage Designs
Yasuhiro Ogasahara, Hanpei Koike (AIST) |
This paper discusses impacts of flexible Vth control, low process variability, and steep SS with small on-current of new... [more] |
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| IEICE-ICD, IEICE-SDM, IST [detail] |
2016-08-03
14:40 |
Osaka |
Central Electric Club |
PN-Body Tied Super Steep SS FET with Body Bias below 1V and Drain Bias 0.1V
Takahiro Yoshida, Jiro Ida, Takashi Horii (KIT), Masao Okihara (Lapis), Yasuo Arai (KEK) |
We have found out that the super steep Subthreshold Slope (SS) of the PN-body tied SOI FET appeared with the body voltag... [more] |
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| IEICE-ICD, IEICE-SDM, IST [detail] |
2016-08-03
15:05 |
Osaka |
Central Electric Club |
Increased Drain-Induced Variability and Within-Device Variability in Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm
Tomoko Mizutani, Kiyoshi Takeuchi, Ryota Suzuki, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) |
The effects of drain voltage in threshold voltage variability in extremely narrow silicon nanowire (NW) channel FETs are... [more] |
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| IEICE-ICD, IEICE-SDM, IST [detail] |
2016-08-03
15:30 |
Osaka |
Central Electric Club |
Performance Enhancement of Tunnel FET by Negative Capacitance
Masaharu Kobayashi, Kyungmin Jang, Nozomu Ueyama, Toshiro Hiramoto (Univ. of Tokyo) |
IoT devices in a sensor network require a new energy-efficient transistor which operates at ultralow voltage and power e... [more] |
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